Characterization and Testing of CMOS Subcircuits in a Mixed Signal IC

In a response to today’s trend in technology, the theoretical focus of most digital and analog based circuit courses is shifting towards CMOS technology. Due to the lack of proper laboratory testing circuits and environments for CMOS technology; older, obsolete circuits are used in many laboratory classes. While these labs afford students the chance to compare classroom analysis to real laboratory results, they fail to provide an accurate portrayal of today’s technology. In an attempt to combat this problem, Dr. James Morizio designed a chip to provide CMOS devices that could be used in an introductory laboratory class. The purpose of this independent study was to design a test fixture that would allow the chips to be tested, to design test circuits that would allow the devices to be tested, to test the functionality of the devices in the laboratory and to compare the laboratory results to HSPICE simulation results, and finally to rewrite the labs for ECE163 using the CMOS devices. The test fixture that allowed all of the devices to be tested was built by Jennifer Wilbur and Jessica Smith. The circuit designs were a collaborative work between Jessica Smith, Jennifer Wilbur, Dr. James Morizio, and Dr. Jeffrey Derby. Laboratory measurements were led by Jennifer Wilbur, while HSPICE simulations were led by Jessica Smith. The circuits tested were the individual NMOS and PMOS devices, the inverter, the current mirror, the common source amplifier, the source follower, the differential pair, and the two stage operational amplifier. Some devices, such as the individual devices and the inverter, yielded similar simulated and experimental results. Other results such as those on the op amp, source follower, and common source amplifier were not as similar but still matched fairly well. For the current mirror and the differential pair no valid experimental results were obtained, as the devices did not work. The end conclusion of this study is that the test CMOS device is neither stable nor reliable enough to be used in the laboratory at this point. Introduction Currently, the electrical engineering program at Duke University relies heavily upon the use of BJT’s in the laboratory as they allow for a fairly simple construction of basic circuits. While BJT’s are no longer a significant focus in the “real world”, they continue to receive a disproportionate focus in the classroom as they are currently the only devices allowing students to have the experience of both analyzing and then running tests on circuits. This laboratory focus upon BJT’s permits less time to be spent on the more dominant CMOS technology. CMOS devices are not as easy to use in lab because of their requirement of being perfectly matched in order to correctly function in circuits. Duke’s Electrical Engineering program searched for solutions to this problem but determined that this is a nationwide problem and that no pre-fabricated devices existed that solved this problem. The chip used in this study was designed by Dr. James Morizio after he collected feedback from Doug Holberg (University of Texas), Dr. Martin Brooke (Georgia Tech), Dr. Bill Richards (Thunderbird Technologies), and Dr. Jeff Derby (IBM) on which devices should be on the circuit. The chip that was designed contains a mix of electronics from beginner Complimentary Metal Oxide (CMOS) circuits to advanced Operational Transconductance Amplifiers (OTA) circuits. Mentor Graphics DA and IC were used to create the device’s design and layout. The chip was fabricated using a 0.5μm double poly, triple level metal, 5V CMOS process from AMI Semiconductor Corp. The device was packaged in an 84 pin PGA ceramic package by Promex Industries, Inc. Five devices were packaged and made available for testing in this study. The goals of this study were to design a test fixture that would allow the chips to be tested, to design test circuits that would allow the devices to be tested, to compare the results from simulations using HSPICE and results found in the laboratory, and to produce a revised laboratory manual for ECE163 that could be used in the Fall of 2005 using the CMOS devices on the chip. The paper begins with a description of general testing methods and then summarizes the tests run on the individual subcircuits. It then reviews the results from both the simulation and laboratory tests for each subcircuit. Finally, the results for each device are analyzed and the problems encountered during this study are examined in the discussion. Procedure and Test Data Simulation and Test Methodology Simulation Extraction method The individual devices were isolated into their own file using Mentor Graphics IC. They were then checked to make sure that they were DRC and LVS clean. Next, ICextract (M) was selected and the distributed option was used to produce a netlist that accounted for the capacitances and resistances present. This generated a spice_out file and a .pex file that were used for the simulation tests on each device. The HSPICE level used by the rules file was level 49. Chip Description Dr. James Morizio designed and produced the chip layout using Mentor Graphics tools. The chip was fabricated by AMI Semiconductor Corporation using a 0.5μm double poly, triple level metal, 5V CMOS process. The five chips used for testing were packaged in a 84 pin PGA84M ceramic package by Promex Industries, Inc.. This is a 1.1” square package. The pins of the packages were arranged on an 11 x 11 pin grid at 0.1" centers. Subcircuits on the chip Tested Subcircuits: Two NMOS devices, Two PMOS devices, Inverter, Current Mirror, Common Source Amplifier, Source Follower, Differential Pair, and Two Stage Operational Amplifier. Other Subcircuits: Current Mirror Amplifier, Two Stage Cascode, Two Stage Fully Differential Cascode, Rail-Rail Amplifier, Cascode Current Mirror, Fixed Taper, and Variable Taper. Construction of Test Fixture The test fixture was built on a 4”x 5” Twin Industries board with 0.037” plated holes. A 13x13 Aries 0.1” socket was soldered on and used to test the various chips. Square test pins were soldered into the board and then connected to the underside of the socket using 30 gauge wire that was then soldered to the underside of the socket and wire wrapped to the test pins. All of the grounds on the chip were tied together and connected to a jack. Laboratory Equipment The laboratory equipment used was: the Agilent 34401A Multimeter, the Agilent E3631A DC Power Supply, the Agilent 33220A Function Generator, the Agilent 54624A Oscilloscope, and the HP 3577B Network Analyzer. Figure 1: Chip Layout Figure 2: Package Pin Out Diagram Figure 3:Top Side of the Test Board Figure 4: Underside of the Test Board Device Layouts, Testing Circuits and Testing Methods All of the devices and circuits were tested in the laboratory and were simulated using HSPICE. In the laboratory the tests were run on all five chips. Labview was used to perform many of the sweeps in the laboratory. The pin outs in the tables in this section refer to the pin out diagram in Figure 2. PMOS The PMOS devices, PMOS1 and PMOS2, are shown in Figure 5. The pin outs for the PMOS devices are shown in Table 1. HSPICE Simulation and Laboratory Testing: VDS was swept from 0V to -5V for VGS set to 0, -1, -2, -3, -4, and -5V and the drain current (ID) was measured. VGS was swept from 0V to -5V with VDS held constant at -5V. These conditions were tested on both PMOS1 and PMOS 2 using outp1 and outp2 respectively. NMOS The NMOS devices, NMOS1 and NMOS2, are shown in Figure 5. The pin outs for the NMOS devices are shown in Table 1. HSPICE Simulation and Laboratory Testing: VDS was swept from 0V to 5V for VGS set to 0, 1, 2, 3, 4, and 5V and the drain current (ID) was measured. VGS was swept from 0V to 5V with VDS held constant at 5V. These conditions were tested on both NMOS1 and NMOS 2 using outn1 and outn2 respectively. Inverter The Inverter design is shown in Figure 6. The pin outs for the Inverter are in Table 2. HSPICE Simulation and Laboratory Testing: INV IN was swept from 0V to 5V and the voltage was measured at INV OUT. Current Mirror The Current Mirror design and testing circuit is shown in Figure 6. The pin outs for the Current Mirror are in Table 2. HSPICE Simulation: The circuit in Figure 7 was set up with R2 at 10Ω and R1 swept from 100 Ω to 1k Ω and the voltages across the resistors were measured. Laboratory Testing: The circuit in Figure 7 was set up with R1=R2=10k Ω and the voltages across the resistors were measured. Common Source Amplifier The design of the Common Source Amplifier as well as the testing circuit used for both the DC and AC testing are shown in Figure 8. The pin outs for the Common Source Amplifier are in Table 4. HSPICE Simulation: The circuit in Figure 8 was set up with the given values and a capacitor of 10pF was connected from CSOUT to GND in order to simulate the capacitance in the oscilloscope probes used in lab. A DC sweep on CSIN was performed from 0 to 5V. An AC sweep was performed using the network analyzer to find the gain and 3dB frequency of the circuit. Laboratory Testing: The circuit in Figure 8 was set up and the same DC and AC tests were performed that were performed in HSPICE simulation. Source Follower The design of the Source Follower as well as the testing circuit used for both the DC and AC testing are shown in Figure 9. The pin outs for the Source Follower are in Table 5. HSPICE Simulation: The circuit in Figure 9 was set up with the given values and a 10 pF capacitor was connected from SFOUT to GND in order to simulate the capacitance in the oscilloscope probes used in lab. A DC sweep on SFIN was performed from 0 to 5V. An AC sweep was performed using the network analyzer to find the gain and 3dB frequency of the circuit. Laboratory Testing: The circuit in Figure 9 was set up and the same DC and AC tests were performed that were performed in HSPICE simulation. Differential Pair The design of the Differential Pair as well as the testing circuit used for both the DC and AC testing are shown in Figure 10. The pin outs for the Differential Pair are in Table 6. HSPICE Simulation: The circuit in Figure 10 was set up with the given values and a 10 pF capacitor was connected from DIFFOUT1 to GND to simulate the capacitance in the oscilloscope probes used in lab. A DC sweep on INNEG1 was performed from 0 to 5V with INPOS1=2.5V. Then a DC sweep on INPOS1 was performed from 0 to 5V with INNEG1=2.5V. An AC sweep was then performed using the network analyzer to find the gain and 3dB frequency of the circuit. Laboratory Testing: The circuit in Figure 10 was set up and the same DC and AC tests were performed that were performed in HSPICE simulation. Two Stage Operational Amplifier The design of the two stage operational amplifier is shown in Figure 11. The testing circuit used for the AC analysis is shown in Figure 12 and the circuit used for the DC analysis is shown in Figure 13. In both of these Figures the OPAMP symbol is used to represent the two stage operational amplifier from Figure 11. The pin outs for the operational amplifier are in Table 7. HSPICE Simulation: In the simulation a10 pF capacitor was connected from OPOUT to GND to simulate the capacitance in the oscilloscope probes that are used in lab. A 10 pF capacitor was connected from OPOUT to GND to simulate the capacitance in the probes that must be used in lab. Laboratory Testing: The circuit in Figure 13 was set up with the given values. A DC sweep was performed on OPINPOS from 0 to 5V with OPINNEG held constant at 2.5V. Then Figure 12 was set up and an AC sweep was then performed using the network analyzer to find the gain and 3dB frequency of the circuit. Figure 5: PMOS and NMOS Design Figure 6:Inverter Design Name Pin PMOSG(G) H2 NWELL(S) G1 outp1(D) J2 outp2(D) J1 NMOSG(G) J2 outn1(D) L1 outn2(D) K1 VDD F2 GND F1 Table 1:PMOS and NMOS pin outs Name Pin INV IN G2 INV OUT G3 VDD F2 GND K2 Table 2: Inverter pin outs Figure 7: Current Mirror Diagram Figure 8:Common Source Amplifier Diagram Name Pin MIR IN J5 MIR OUT L5 VDD K7 GND L7 Table 3:Current Mirror Pin Out Name Pin CSIN K4 CSBIAS L2 CSOUT L3 VDD K3 GND L7 Table 4:Common Source Pin Out Figure 9: Source Follower Diagram Figure 10: Differential Pair Diagram Name Pin SFIN L4 SFBIAS K6 SFOUT K5 VDD K7 GND L7 Table 5: Source Follower Pin Out Name Pin INNEG1 E3 INPOS1 E1 VREF F3 DIFFOUT1 E2 VDD F2 GND F1 Table 6: Differential Pair Pin Out Figure 11: Two Stage Op Amp Figure 12: Two Stage Op Amp (AC Analysis) Name Pin OPINPOS B1 OPINNEG C1 OPBIAS D2 OPOUT C2 VDD B2 GND D1 Table 7: Two Stage Op Amp Figure 13: Two Stage Op Amp (DC Analysis)